Esphome logging broken on esp32-h2?

I am following Thread working on ESP32-H2 - Example Project to configure an esp32-h2 “SuperMini” board as a Thread node. Logging doesn’t seem to work right for me.

When I use that configuration yaml, customized for my specific Thread network, I can see the ESP show up in the neighbor table in ot-ctl on the border router. So I know it’s working in some capacity. I just don’t know what exactly it’s doing. I also can’t see other important operational details like the autogenerated IPv6 address.

I would like to keep tweaking this configuration to get the esp32-h2 to do what I want: mmWave sensors, BME280 sensors, IR blasters, etc. Logging is a critical part of this task, and I can’t get it to work.

On my other ESP boards, I can flash a trivial esphome configuration enabling verbose log output and clearly see where the “handoff” happens:

% cat c3-test.yaml
esphome:
  name: c3-test
  friendly_name: c3-test
  platformio_options:
    board_build.flash_mode: dio

esp32:
  board: esp32-c3-devkitm-1
  variant: ESP32C3
  framework:
    type: esp-idf

# Enable logging
logger:
  level: VERBOSE

% esphome logs -r --device /dev/cu.usbmodem2101 c3-test.yaml
INFO ESPHome 2025.11.5
INFO Reading configuration c3-test.yaml...
INFO Starting log output from /dev/cu.usbmodem2101 with baud rate 115200
[11:42:58.425]rst:0x15 (USB_UART_CHIP_RESET),boot:0xd (SPI_FAST_FLASH_BOOT)
[11:42:58.425]Saved PC:0x40381762
WARNING Decoded 0x40381762: rv_utils_wait_for_intr at /Users/admin/.platformio/packages/framework-espidf/components/riscv/include/riscv/rv_utils.h:79
 (inlined by) esp_cpu_wait_for_intr at /Users/admin/.platformio/packages/framework-espidf/components/esp_hw_support/cpu.c:62
[11:42:58.465]SPIWP:0xee
[11:42:58.465]mode:DIO, clock div:1
[11:42:58.465]load:0x3fcd5830,len:0x15ac
[11:42:58.465]load:0x403cbf10,len:0xba4
[11:42:58.465]load:0x403ce710,len:0x3020
[11:42:58.465]entry 0x403cbf10
[11:42:58.465]I (24) boot: ESP-IDF 5.5.1 2nd stage bootloader
[11:42:58.465]I (24) boot: compile time Dec 13 2025 11:28:59
[11:42:58.465]I (24) boot: chip revision: v0.4
[11:42:58.465]I (25) boot: efuse block revision: v1.3
[11:42:58.465]I (25) boot.esp32c3: SPI Speed      : 80MHz
[11:42:58.466]I (25) boot.esp32c3: SPI Mode       : DIO
[11:42:58.466]I (25) boot.esp32c3: SPI Flash Size : 4MB
[11:42:58.466]I (25) boot: Enabling RNG early entropy source...
[11:42:58.466]I (25) boot: Partition Table:
[11:42:58.466]I (25) boot: ## Label            Usage          Type ST Offset   Length
[11:42:58.466]I (26) boot:  0 otadata          OTA data         01 00 00009000 00002000
[11:42:58.466]I (26) boot:  1 phy_init         RF data          01 01 0000b000 00001000
[11:42:58.466]I (26) boot:  2 app0             OTA app          00 10 00010000 001c0000
[11:42:58.467]I (26) boot:  3 app1             OTA app          00 11 001d0000 001c0000
[11:42:58.467]I (27) boot:  4 nvs              WiFi data        01 02 00390000 0006d000
[11:42:58.467]I (27) boot: End of partition table
[11:42:58.467]I (27) esp_image: segment 0: paddr=00010020 vaddr=3c030020 size=0a8d4h ( 43220) map
[11:42:58.467]I (34) esp_image: segment 1: paddr=0001a8fc vaddr=3fc8bc00 size=01354h (  4948) load
[11:42:58.467]I (36) esp_image: segment 2: paddr=0001bc58 vaddr=40380000 size=043c0h ( 17344) load
[11:42:58.467]I (39) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=21cc4h (138436) map
[11:42:58.486]I (61) esp_image: segment 4: paddr=00041cec vaddr=403843c0 size=07740h ( 30528) load
[11:42:58.491]I (67) esp_image: segment 5: paddr=00049434 vaddr=50000000 size=00020h (    32) load
[11:42:58.495]I (71) boot: Loaded app from partition at offset 0x10000
[11:42:58.495]I (71) boot: Disabling RNG early entropy source...
[11:42:58.575][I][logger:121]: Log initialized
[11:42:58.576][I][app:073]: Running through setup()
[11:42:58.576][V][app:074]: Sorting components by setup priority
[11:42:58.577][V][component:166]: Setup preferences
[11:42:58.578][V][scheduler:144]: Scheduler interval for  is 60000ms, offset 3678ms
[11:42:58.578][C][component:173]: Setup preferences took 1ms
[11:42:58.579][I][app:120]: setup() finished successfully!
[11:42:58.580][I][app:190]: ESPHome version 2025.11.5 compiled on Dec 13 2025, 11:28:44
[11:42:58.580][C][logger:261]: Logger:
[11:42:58.581][C][logger:261]:   Max Level: VERBOSE
[11:42:58.581][C][logger:261]:   Initial Level: VERBOSE
[11:42:58.581][C][logger:267]:   Log Baud Rate: 115200
[11:42:58.581][C][logger:267]:   Hardware UART: USB_SERIAL_JTAG
[11:42:58.582][C][logger:274]:   Task Log Buffer Size: 768

But on the H2 it “goes dark”:

% cat h2-test.yaml
esphome:
   name: h2-test
   friendly_name: h2-test

esp32:
  board: esp32-h2-devkitm-1
  variant: ESP32H2
  framework:
    type: esp-idf

# Enable logging
logger:
  level: VERBOSE

% esphome logs -r --device /dev/cu.usbmodem2101 h2-test.yaml
INFO ESPHome 2025.11.5
INFO Reading configuration h2-test.yaml...
INFO Starting log output from /dev/cu.usbmodem2101 with baud rate 115200
[11:40:47.923]rst:0x15 (USB_UART_HPSYS),boot:0x8 (SPI_FAST_FLASH_BOOT)
[11:40:47.923]Saved PC:0x40801cac
WARNING Decoded 0x40801cac: rv_utils_wait_for_intr at /Users/admin/.platformio/packages/framework-espidf/components/riscv/include/riscv/rv_utils.h:79
 (inlined by) esp_cpu_wait_for_intr at /Users/admin/.platformio/packages/framework-espidf/components/esp_hw_support/cpu.c:62
[11:40:47.962]SPIWP:0xee
[11:40:47.962]mode:DIO, clock div:1
[11:40:47.962]load:0x408460f0,len:0x1700
[11:40:47.963]load:0x4083c2d0,len:0xf78
[11:40:47.963]load:0x4083efd0,len:0x2fd8
[11:40:47.963]entry 0x4083c2d0
[11:40:47.963]I (23) boot: ESP-IDF 5.5.1 2nd stage bootloader
[11:40:47.963]I (23) boot: compile time Dec 13 2025 11:19:40
[11:40:47.963]I (24) boot: chip revision: v0.1
[11:40:47.963]I (25) boot: efuse block revision: v0.3
[11:40:47.963]I (26) boot.esp32h2: SPI Speed      : 64MHz
[11:40:47.963]I (30) boot.esp32h2: SPI Mode       : DIO
[11:40:47.963]I (34) boot.esp32h2: SPI Flash Size : 4MB
[11:40:47.965]I (38) boot: Enabling RNG early entropy source...
[11:40:47.967]I (42) boot: Partition Table:
[11:40:47.974]I (45) boot: ## Label            Usage          Type ST Offset   Length
[11:40:47.980]I (51) boot:  0 otadata          OTA data         01 00 00009000 00002000
[11:40:47.987]I (58) boot:  1 phy_init         RF data          01 01 0000b000 00001000
[11:40:47.993]I (64) boot:  2 app0             OTA app          00 10 00010000 001c0000
[11:40:48.000]I (71) boot:  3 app1             OTA app          00 11 001d0000 001c0000
[11:40:48.006]I (77) boot:  4 nvs              WiFi data        01 02 00390000 0006d000
[11:40:48.009]I (84) boot: End of partition table
[11:40:48.017]I (87) esp_image: segment 0: paddr=00010020 vaddr=42030020 size=0b078h ( 45176) map
[11:40:48.030]I (106) esp_image: segment 1: paddr=0001b0a0 vaddr=40800000 size=04f78h ( 20344) load
[11:40:48.037]I (113) esp_image: segment 2: paddr=00020020 vaddr=42000020 size=232e8h (144104) map
[11:40:48.075]I (151) esp_image: segment 3: paddr=00043310 vaddr=40804f78 size=05e0ch ( 24076) load
[11:40:48.083]I (159) esp_image: segment 4: paddr=00049124 vaddr=4080ad90 size=016fch (  5884) load
[11:40:48.088]I (165) boot: Loaded app from partition at offset 0x10000
[11:40:48.089]I (166) boot: Disabling RNG early entropy source...

Any ideas why? The one thing I tried was manually overriding baud_rate to 115200, which did nothing.

Two more observations:

  1. No such problem was seen on esp32-c6. Only on esp32-h2.
  2. Even with logging set to VERY_VERBOSE on esp32-c6, the openthread component doesn’t log much at all. No packet activity, not even IPv6 addresses.

The exact model of board used should be specified in your post if you want us to help.

As stated above it is an esp32-h2 Super Mini. It looks exactly like ESP32-H2 Super Mini Development Board Details, Pinout, Specs . It was purchased from https://www.aliexpress.us/item/3256807802657001.html

Alleged schematic, from https://ziliao.nologo.tech/无名科技Nologo资料/ESP32开发板/ESP32-H2%20Supermini+HXB资料/SuperMini-H2原理图.png

Try setting hardware_uart: USB_SERIAL_JTAG, it looks like the default for H2 is not set.

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